1. Field of the Invention
Present invention relates to a control method of a semiconductor memory device and the semiconductor memory device having a successive data access operation, and in particular, a control method of a semiconductor memory device and the semiconductor memory device in which a pre-charge operation is required after completion of the successive access operation.
2. Description of the Related Art
Along with recent development of digital technologies, other than personal computers, digital appliances such as digital cameras, portable telephones and so on have been handling a lot of data such as image data and so on. As for retrieval and record of the image data, high-speed read-out and write of a lot of successive data is required. Consequently, a semiconductor memory device such as DRAM and so on carries out a high-speed successive access operation as follows. That is, there is used a high speed successive access operation such as a page operation, a burst operation and so on, wherein a predetermined word line is activated and data access is carried out sequentially to a memory-cell group which is selected by the word line. Here, as for the high-speed data access, it is necessary to shorten cycle time that is sum of an access operation period during the successive access operation and a pre-charge operation period at the time of completion of the successive access operation.
FIG. 12 shows a circuit block diagram of a data-input/output path in a semiconductor memory device. On the occasion of the successive data access, any one of predetermined word lines (WL0, WL1, . . . ) is activated, and data of the selected memory-cell group is differentially amplified in respective bit line pairs (BL0 and /BL0, BL1 and /BL1, . . . ). After the initiation of the differential amplification, the successive access operation is initiated. In response to column addresses, column selecting lines (CL0, CL1, . . . ) are selected sequentially. That is, corresponding transfer gates (T0Z and T0X, T1Z and T1X, . . . ) are made to be conductive sequentially and the bit line pair is connected to a data line pair (DB and /DB) so that the successive data access operation is carried out. The access operation here includes both operations of a readout operation and a write operation. Selected column addresses can be configured that they are inputted from outside sequentially and can be also configured that they are automatically set in a predetermined order.
On the occasion of completion of the successive access operation, it is necessary that, after the selected word line is deactivated so that the memory cell is separated from the bit line, each of the bit line pair (BL0 and /BL0, BL1 and /BL1, . . . ) is equalized in preparation of a next cycle. This control is carried out by a pre-charge control section 100. On the occasion of completion of the successive access operation, when a pre-charge signal PRE is inputted, a word line deactivating signal WLRSTX is outputted from a word lien deactivating circuit WLR. At the same time, a delay circuit A (DA) times deactivation time of the word line (delay time τA) and outputs a signal φDA. The signal φDA is inputted to a sense amplifier deactivating circuit SAR and a sense amplifier deactivating signal SARSTX is outputted. Further, a delay circuit B (DB) times deactivation time of a sense amplifier (delay time τB) and outputs a signal φDB. The signal φDB is inputted to a bit line equalizing circuit BLR and a bit line equalizing signal BLRSTX is outputted.
An appearance of the successive access operation is shown in FIG. 13. Respective bit linepairs (BL0 and /BL0, BL1 and/BL1, . . . ) are differentially amplified and in contrast, the data line pair (DB and /DB) is amplitude-limited in voltage. Since (½) VCC voltage is set as a central value, on the occasion of connection by column selecting lines (CL0, CCL1, . . . ), disturb phenomenon occurs in the bit line. That is, an electric potential moves from the data line to the bit line of low voltage level so that the voltage level is increased, and an electric potential moves from the bit line of high voltage level to the data line so that the voltage level is decreased. This situation is restored by the sense amplifier after the separation of the data line.
The pre-charge period is classified into three time regions of the word line deactivation time τA for separating the memory cell from the bit line, the sense amplifier deactivation time τB and bit line pair equalizing time τC.
Japanese Laid-open Patent Publication No.10-312684 discloses a countermeasure as for shortening of the pre-charge period. FIG. 14 shows a circuit block diagram and FIG. 15 shows operational waveforms at the time of data read-out.
In the circuit block described in the Japanese Laid-open Patent Publication No.10-312684 shown in FIG. 14, a first cell side bit line BLC is connected to one end of a first transfer gate 105, and a first sense amplifier side bit line BLS is connected to the other end of the first transfer gate 105, and a second cell side bit line *BLC is connected to one end of a second transfer gate 115 and a second sense amplifier side bit line *BLS is connected to the other end of the second transfer gate 115, and memory cells 120 and 130 that are selected by word lines WL0 and WL1 are connected to the first and second cell side bit lines BLC and *BLC, respectively, and a sense amplifier 170 is connected between the first sense amplifier side bit line BLS and the second sense amplifier side bit line *BLS.
A data read-out operation from the memory cell 120 or 130 is as shown in FIG. 15. Firstly, when the first transfer gate 105 and the second transfer gate 115 are opened, the sense amplifier 170 is activated and an electric potential difference of the first sense amplifier side bit line BLS and the second sense amplifier side bit line *BLS is amplified. After the word lines WL0 and WL1 are deactivated, the first transfer gate 105 and the second transfer gate 115 are closed. At this time, the first memory cell side bit line BLC and the second memory cell side bit line *BLC are set to be of bit line reset potential VSS, and in parallel to this, signals on the first and second sense amplifier side bit lines BLS and *BLS are outputted.
Hereby, in case of data read-out, in advance of signal outputting from the first and second sense amplifier side bit lines BLS and *BLS, deactivation of the word lines WL0 and WL1 is already carried out. Therefore, during the pre-charge period, it is not necessary to carry out the deactivating operation of the word lines WL0 and WL1.
However, the semiconductor memory device of FIG. 12 needs a good deal of time as to the deactivating operation of the word lines which are carried out during the pre-charge period and the equalizing operation of the bit line pairs, which is a problem. This is because a lot of the memory cells are connected to both the word lines and the bit lines and length of wiring is very long. That is, it is because parasitic capacity due to the memory cells and wire resistance due to the wiring become a great deal and large time constant is required for voltage transition.
Based upon future trend of larger memory capacity design, the number of memory cells which are connected to the word lines and the bit lines is increased, and based upon this, there is a trend that wire length is lengthened. Further, it is expected that time constant in voltage transition of the word lines and the bit lines is lengthened more and more. There is a possibility that, as for the shortened access period by the high-speed successive access operation, shortening of the pre-charge-period becomes insufficient and increase of cycle time is invited. There is a possibility that, because of the increase of cycle time, data access speed is limited. Further, there is a possibility that the proportion of the pre-charge period in the cycle time is relatively increased and thereby, rate of data access cannot be raised. There is a possibility that high speed and high efficiency data access request cannot be satisfied, which is a problem.
In Japanese Laid-open Patent Publication No.10-312684, deactivation of the word lines is carried out in advance of signal outputting from the bit line pair BLS and *BLS. Hereby, there occurs no necessity that the deactivation of the word lines is carried out during the pre-charge period, and it is possible to try to shorten the pre-charge period. However, in this case, the signal outputting from the bit line pair BLS and *BLS is carried out after the deactivation of the word lines, which is a problem.
That is, after the differential amplification of the bit line pair BLC and *BLC is completed and data is restored in the memory cell, it is necessary to carry out the deactivation of the word lines. Therefore, under normal circumstances, initiation of the read-out operation of first data that can be read out before the differential amplification of the bit line pair is completed is delayed. There is a possibility that high speed data access request cannot be satisfied, which is a problem.
Further, Japanese Laid-open Patent Publication No.10-312684 is of such content that, in advance of the read-out operation, the deactivation of the word lines is carried out and thereby, the deactivation of the word lines during the pre-charge period is eliminated. Since the word lines are deactivated in advance, it cannot apply to a write operation and there is a possibility that it cannot apply to the shortening of the pre-charge period after the write operation, which is a problem.